Field of the Invention
The present invention relates to a polishing method and apparatus for polishing a film formed on a substrate such as a semiconductor wafer by pressing the substrate against a polishing pad while moving the substrate and the polishing pad relative to each other.
Description of the Related Art
In recent years, high integration and high density in semiconductor device demands smaller and smaller wiring patterns or interconnections and also more and more interconnection layers. Multilayer interconnections in smaller circuits result in greater steps which reflect surface irregularities on lower interconnection layers. An increase in the number of interconnection layers makes film coating performance (step coverage) poor over stepped configurations of thin films. Therefore, better multilayer interconnections need to have the improved step coverage and proper surface planarization. Further, since the depth of focus of a photolithographic optical system is smaller with miniaturization of a photolithographic process, a surface of the semiconductor device needs to be planarized such that irregular steps on the surface of the semiconductor device will fall within the depth of focus.
Thus, in a manufacturing process of a semiconductor device, it increasingly becomes important to planarize a surface of the semiconductor device. One of the most important planarizing technologies is chemical mechanical polishing (CMP). Thus, there has been employed a chemical mechanical polishing apparatus for planarizing a surface of a semiconductor wafer. In the chemical mechanical polishing apparatus, while a polishing liquid containing abrasive particles such as silica (SiO2) therein is supplied onto a polishing surface of a polishing pad, a substrate such as a semiconductor wafer is brought into sliding contact with the polishing surface, so that a film formed on the substrate is polished.
This type of polishing apparatus includes a polishing table having a polishing pad, and a top ring for holding a substrate such as a semiconductor wafer. The polishing apparatus generally has a retainer ring at an outer circumferential side of the substrate for pressing the polishing pad. When the film formed on the substrate is polished using such a polishing apparatus, the substrate is held and pressed against the polishing pad under a predetermined pressure by the top ring. At this time, while a polishing liquid is supplied onto the polishing pad, the polishing pad and the top ring are moved relative to each other to bring the film on the substrate into sliding contact with the polishing pad in the presence of the polishing liquid, so that the film on the substrate is polished to a flat mirror finish.
It has been known that in the polishing process using a polishing pad comprising IC-1000/SUBA400 (two-layer cloth), for example, polishing performance (polishing rate or polishing profile) is liable to be varied due to a change in properties of the polishing pad such as wear of the upper layer (IC-1000) of the polishing pad.
FIG. 1 is a graph showing an example of the relationship between a thickness of a polishing pad (IC-1000) and a polishing rate in a polishing process. As shown in FIG. 1, as the thickness of the polishing pad is thinner, the polishing rate increases. FIG. 2 is a graph showing an example of non-dimensional polishing rate with respect to radial positions on a substrate when the film on the substrate is polished by using polishing pads (IC-1000) having different thicknesses, 32 mils, 50 mils and 80 mils. As shown in FIG. 2, the polishing profile differs with the thickness of the polishing pad.
Therefore, in order to maintain a constant polishing amount and a constant polishing profile for a film, it is necessary to appropriately change polishing conditions, such as a polishing time and a polishing pressure, according to a decrease in the thickness of the polishing pad, for example, when the thickness of the polishing pad has decreased (worn) by dressing of the polishing pad by means of a dresser.
Conventionally, as a method for cancelling variation in the polishing performance caused by such a conditional change of the polishing pad, closed-loop control (CLC) using an ITM (in-line thickness monitor) or an R-ECM (eddy current monitor) is commonly used.
However, in the case of the CLC using an ITM, it is necessary to take a substrate such as a semiconductor wafer out of a polishing section, and clean and dry the substrate every time the surface condition of the substrate is measured. Therefore, a series of operations for such measurement requires a lot of time, resulting in a decreased throughput. Further, the CLC method using an R-ECM can be applied only when a film to be polished is a metal film. For example, in a polishing process of a copper film formed on a substrate, the second-step polishing (touch-up) after the removal of the copper film from the substrate surface has been practiced in a “blind” polishing manner under fixed polishing conditions and a fixed polishing time. Thus, variation in the polishing performance caused by a conditional change of the polishing pad has an effect on the polishing result of the substrate, leading to a lowering of the productivity. Also in the polishing process of a metal film to which the CLC method using an R-ECM can be applied, the introduction of a system to perform such control method requires a great deal of expenses.
The applicant of the present invention has proposed a polishing apparatus in which the amount of wear of a wearing member such as a polishing pad is calculated to determine whether a polishing process is being performed in a normal manner, or correlation data showing a correlation between the amount of wear of a wearing member such as a polishing pad and a polishing profile are accumulated to appropriately control polishing conditions (see Japanese Laid-Open Patent Publication No. 2006-255851), and a polishing apparatus in which polishing conditions are changed according to a change in the profile of a polishing pad (see Japanese Laid-Open Patent Publication No. 2009-148877).
The applicant of the present invention has also proposed a substrate polishing method and apparatus in which the relationship between the thickness of a polishing pad and the polishing rate during the period immediately after replacement of a polishing pad until subsequent replacement of a polishing pad is determined in advance, and the polishing time for the next substrate is optimized based on the thickness of the polishing pad actually measured (see Japanese Laid-Open Patent Publication No. 2005-347568).
There has been proposed a method for planarizing a surface of a semiconductor wafer which includes a step of measuring the rate of removal of a wafer material from a wafer, and a step of providing a model that clarifies the effects on polishing effectiveness caused by the conditions of a tool, such as the wear of the tool, variation of the tool with time from the use of the tool, and the like (see U.S. Pat. No. 7,160,739 B2).
Further, there have been proposed a method for determining the life of a polishing pad in which the thickness of a polishing pad is measured, and when the measured thickness reaches a predetermined value or less, the polishing pad is judged to reach the end of its life (see Japanese Laid-Open Patent Publication No. 2004-25413), and a polishing apparatus in which the profile of a polishing pad is controlled by changing dressing conditions for the polishing pad (see Japanese Laid-Open Patent Publication No. 2004-47876).
Furthermore, there have been proposed a polishing apparatus in which dressing conditions are changed to obtain a desired polishing rate when a change in the cut rate by dressing of the polishing pad has occurred (see U.S. Pat. Nos. 5,609,718, 5,801,066, and 5,655,951), and a polishing apparatus in which an estimated polishing rate is calculated by substituting a measurement value of the remaining thickness of the polishing pad into a model equation prepared by multiple regression analysis of the thickness of a polishing pad and the actual polishing rate, and a process abnormality is judged by determining whether or not the estimated polishing rate falls within a predetermined range (see Japanese Laid-Open Patent Publication No. 2005-342841).